The present invention relates to metal insulator semiconductor field effect transistors (MISFET).
Complementary Metal-Oxide Semiconductor (CMOS), has been the semiconductor technology of choice since the late 1970""s, and in 1998 the 0.25 micron CMOS technology generation is in production. There are many reasons to choose CMOS over other technologies. The most important is the reduced power consumption, because the basic building block of circuits for binary logic, the CMOS xe2x80x9cInverterxe2x80x9d, only consumes power when changing logic states.
The fundamental factors determining the performance of standard xe2x80x9cPlanar Technologyxe2x80x9d, are the channel length of the MOSFETs, and the parasitic capacitances. For deep sub-micron CMOS, as the gate lengths get shorter, leakage current tends to get higher, and the overall process technology becomes more complex. Not only the number of processing steps increases, but the complexity and difficulty of some of those steps is also increased. Since to make CMOS circuits, NMOS and PMOS devices are needed, many Front-End processing steps have to be made twice, separately for each device type.
However, CMOS circuits can also be made with other MOSFET architectures, like Vertical MOSFETs (see reference [1]). The perspectives opened by Vertical MOSFETs are very attractive. That is especially true when considering the technological and fundamental physical limitations facing conventional (Planar) MOSFETs for gate lengths below 100 nm. For Vertical MOSFETs the channel length is defined by the doping and/or heterojunction profiles, made by low temperature epitaxy. Lithography defines the cross section of the devices (channel width), and therefore the density of integration.
The present invention pertains to the field of Complementary Metal-Insulator-Semiconductor Field-Effect Transistors (C-MISFETs). Since the most common insulator is an oxide (silicon dioxide), these devices are almost always designated by Complementary Metal-Oxide-Semiconductor Field-Effect Transistors (C-MOSFETs). More specifically, it pertains to CMOS circuits made with a new kind of Vertical MOSFETs.
The present invention, introduces a MOSFET device, that behaves as N- or P-type transistor, depending only on the applied bias. Setting of the source voltage supply, determines if the device will behave as a NMOS or as a PMOS. For positive drain to source (VDS) and gate to source (VGS) voltages, the device behaves as NMOS. For negative drain to source (VDS) and gate to source (VGS) voltages, the same device acts like a PMOS. Therefore, with the device of the present invention it is possible to make complementary circuits (CMOS), even though only a single device type is fabricated, which xe2x80x9ca priorixe2x80x9d is neither N- or P-type.
The subject of this invention will hereafter be designated by xe2x80x9cSingle Device Complementary Metal Oxide Semiconductor Field Effect Transistorxe2x80x9d, or SD-CMOS.
The independence of channel length from lithography, and the kind of doping/heterojunction profiles possible with low temperature epitaxy, enables the fabrication of Vertical MOSFETs with channels only tens of nanometers long, and with atomic layer control across the entire wafer. The limitations to make Vertical MOSFETs with very short channel lengths, will no longer be technological, but related to device physics.
Vertical MOSFETs, have an intrinsic advantage over horizontal MOSFETs: it is straightforward to build an asymmetry of the source to channel junction, versus the channel to drain junction. With horizontal MOSFETs, it is also possible to introduce asymmetry, but that comes at a cost in terms of process complexity (extra masks to differentiate source from drain for each type of device). And in any case, the doping and/or heterojunction profiles (made by ion implantation) can never come close to what low temperature epitaxy has demonstrated.
Like with Horizontal homojunction MOSFETs, Vertical homojunction MOSFETs suffer from Short Channel Effect (SCE), albeit at shorter channel lengths due to the ability to have sharper doping profiles, and therefore reduced depletion widths. Numerical simulations of a xe2x80x9cPlanar-Dopedxe2x80x9d Vertical MOSFET with a 50 nm channel length, predict very high performance levels (see reference [2]). But as channel length is further reduced, higher doping levels are needed to keep the electrostatic barrier between source and channel. In the limit, even without any bias (at the drain or gate), the built-in electric field, induces band to band tunneling through the source to channel barrier. Naturally, the necessity of applying drain bias, leads to even stronger scaling limitations due to Drain Induced Barrier Lowering (DIBL). For these reasons, it has been predicted (see reference [1]), that due to SCE and DIBL, the practical limit for how short channels can be, is around 80 nm.
An alternative type of Vertical MOSFETs, the Vertical Heterojunction MOSFETs (VH-MOSFETs), uses heterojunctions instead of homojunctions to build the source to channel electrostatic barrier (see reference [3]). Because the potential barrier is originated by a heterojunction, there is no need to introduce doping in the channel to make the barrier, and therefore the device is, by definition xe2x80x9cfully depletedxe2x80x9d. Also the heterojunction barrier exists across the entire channel thickness, and therefore removes any restriction on the distance between gates. With this device architecture, simulations show that ultra-short channels are possible (down to 10 nm), without suffering from SCE or DIBL (see reference [3]). The device type (NMOS or PMOS) is defined by what type of dopant is incorporated in the source and drain regions.
Numerical simulations of Double-Gate SOI CMOS with 30 nm gate/channel lengths (see reference [4]), predict extraordinary performance levels. A very illustrative parameter is the CMOS ring oscillator delay being less than 1 picosecond. Equal or better performance levels should be expected for the VH-MOSFET with channel lengths like 20 nm for example.
CMOS integration schemes have been proposed (see reference [3]), where the device layers of one device type are stacked on the device layers of the other device type, thereby enabling a single epitaxial growth step, and a common gate stack (gate insulator and gate electrode). Such integration schemes offer the perspective of significant overall front-end process simplification, and area gains, over configurations where NMOS and PMOS transistors would be made xe2x80x9cside by sidexe2x80x9d.
Vertical MOSFETs have yet other attractive features. It has been shown how Vertical MOSFETs make possible memory cells, with a quarter of the area of cells made with planar MOSFETs, for the same generation of lithography equipment (see references [5, 6, 7]). For decades, DRAM has driven the progress in process technology. When optical lithography finds its ultimate limitations (believed to be around 100 nm), it is very likely that cells made with Vertical MOSFETs will be seriously considered as viable alternatives to increase the bit density.
However, and assuming that the capability of making Vertical MOSFETs with very short channels is to be fully exploited, it is required to have very low temperature processing (typically, below the temperature at which dopants will start to significantly diffuse and/or strained layers relax). Vertical MOSFETs, regardless of their channel length and particular device layer composition/profile, different device regions like gate, have source and drain lying on different planes. Therefore contacts to these regions (and to gate electrode) must be made by separate sequences of contact hole formation and contact hole filling with a metal.
It is an object of the present invention to improve the manufacturing process of MISFET""s.
This object is achieved by providing a metal insulator semiconductor field effect transistor (MISFET) comprising:
a source layer being made with a material having a source band gap (EG2) and a source mid-gap value (EGM2), said source layer having a source Fermi-Level (EF2);
a drain layer having a drain Fermi-Level (EF4);
a channel layer between the source layer and the drain layer, said channel layer being made with a material having a channel band gap (EG3) and a channel mid-gap value (EGM3), said channel layer having a channel Fermi level (EF3);
a source contact layer connected to the source layer opposite the channel layer, said source contact layer having a source contact Fermi-Level (EF1); and
a gate electrode having a gate electrode Fermi-Level (EF6) wherein:
said source band gap is substantially narrower (EG2) than said channel band gap (EG3);
said source contact Fermi-Level (EF1), said source Fermi-Level (EF2), said channel Fermi-Level (EF3), said drain Fermi-Level (EF4) and said gate electrode Fermi-Level (EF6) are equal to said source mid-gap value (EGM2) and said channel mid-gap value (EGM3), within a predetermined tolerance value, when no voltage is applied to the device.
By providing that the Fermi-Levels are substantially equal to the source and the channel mid-gap values, symmetric paths from source to drain for electrons and for holes are created. This allows the device to behave as an NMOS or PMOS, depending on the voltage applied. It substantially improves the manufacturing process of MISFET""s, since it is no longer necessary to decide, contrary to known devices hitherto, upon fabrication if the device should behave as NMOS or as PMOS. ($$$ please mention here all other advantages)